The present invention relates to a method for manufacturing three-dimensional semiconductor devices and, more particularly, to an interconnection between the elements of different layers in such a three-dimensional semiconductor device.
A semiconductor device and particularly an integrated circuit formed on a semiconductor substrate has been formed by arraying elements two-dimensionally on the substrate by means of an oxidation, a diffusion, an ion implantation, a CVD, a photolithography, etc. known per se of conventional technique. Such a two-dimensional element array in the conventional integrated circuit has had its limit in high integration and high-speed operation of the semiconductor device. It has been proposed as an overstep of this limit a so-called a three-dimensional integrated circuit in which elements have been stacked or laminated in a multilayer. As a substrate which realizes this three-dimensional integrated circuit, a multilayer substrate which has been prepared by irradiating an energy beam such as a laser beam or an electron beam to a polycrystalline silicon layer or an amorphous silicon layer to form a large grain crystal granulation or single crystallization and laminating such layers has been desirably contrived.
The conventional method for manufacturing the substrate of a three-dimensional semiconductor device which have been heretofore proposed can be largely classified into the following three:
1. SOI (Silicon On Insulator)
In the SOI method, an insulating film such as an SiO.sub.2, SiN, etc. is deposited on a silicon substrate, a polycrystalline or amorphous silicon is deposited thereon, and a continuous laser beam or an electron beam is irradiated to the polycrystalline or amorphous silicon to thereby form a silicon layer of large crystal grains. According to this SIO method, it enables the formation of crystal grains having approx. 100 .mu.m in diameter. When integrated circuit elements are, however, formed on the silicon layer which includes such crystal grains, some of these elements are formed across the crystal grain boundary, and the electrical property of these elements across the grain boundary deteriorates as compared with the most other elements. Therefore, the performance of the entire integrated circuit is largely lowered.
2. Graphoepitaxy
In the graphoepitaxy, in infinitesimal groove is formed on the surface of an insulating film such as an SiO.sub.2, SiN, etc., a polycrystalline or amorphous silicon film is deposited on the insulating film, and an energy beam is irradiated to the polycrystalline or amorphous silicon film similarly to the SOI method to thereby increase the crystal grains of the silicon layer. According to this graphoepitaxial method, it is capable of obtaining crystal grains larger in diameter than those formed by the SOI method, but since the substrate of the three-dimensional semiconductor device thus formed also has a crystal grain boundary, it also has drawbacks similar to those of the substrate of the semiconductor device formed by the SOI method in practical use.
3. LESS (Lateral Epitaxy by Seeded Silicon)
In the LESS method, an opening is, as shown in FIG. 1, formed at a part of an insulating film 2 formed on a silicon substrate 1, a polycrystalline or amorphous silicon film 3 is deposited on the insulating film 2, and a continuous beam 4 such as a laser beam or an electron beam is irradiated to the silicon film 3 to thereby grow a crystal laterally from a single-crystalline silicon substrate as a seed crystal contacted through the opening with the silicon film 3. In this case, a single crystal region extends laterally from the opening upto the maximum or approx. 100 .mu.m. This LESS method has an advantage such that the single crystal region can be formed at a desired location of the poly- or amorphous silicon film, i.e., a semiconductor element can be always formed in the single crystal region.
Among the above-described three methods, the LESS method in the above paragraph 3 is considered to be most desirable. However, the LESS method still has such drawbacks that it is necessary to provide a number of openings in which seed crystals exist and yet the part of the deposited silicon film formed at the opening becomes recess, in which a preferable element cannot be formed, resulting in an obstacle in enhancing the integration of the three-dimensional semiconductor device.
Further, in the case of manufacturing a three-dimensional integrated circuit, it is another important problem to establish a wiring technique for wiring between the elements formed on different crystal layers. Particularly when an interval between the elements is reduced so as to increase the integration of the three-dimensional integrated circuit, there unavoidably occurs an abrupt stepwise difference between the elements due to the thickness of the insulating film and the thickness of the semiconductor layer, resulting in the stepwise disconnection of the interconnection between the elements as further drawback.